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Title:
PHASE DISCRIMINATION CIRCUIT
Document Type and Number:
Japanese Patent JPS61172070
Kind Code:
A
Abstract:

PURPOSE: To easily detect the phase difference of a plurality of signals with high accuracy, by converting two or more of signals, of which the phases must be detected, to state signals before and behind a reference time signal and analyzing the advance and delay thereof.

CONSTITUTION: A plurality of digital signals Sa, Sb to be subjected to the detection of phase difference are made synchronous to a reference signal with definite cycle by a synchronizing circuit 6 and compared with state signals synchronized by an advance and delay analytical circuit 10 to analyze advance or delay and an output signal is sent to a count control circuit 20. A measuring section control circuit 12 performs the control of a measuring section through the comparison with each state signal to apply a count permissible signal to the circuit 20 which, in turn, outputs an advance count section indicating signal Cu or a delay count section indicating signal Cd to a phase count circuit 22 corresponding to the above-mentioned signals. The circuit 22 counts the reference time signal CK from a clock oscillator 8 in a positive or negative direction corresponding to said signals Cu, Cd and generates count value frequency corresponding to the phase difference between the input signals Sa, Sb and count value output is taken from an output terminal 24.


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Inventors:
ASAKAWA TERUO
MOCHIZUKI SHUJI
Application Number:
JP1312885A
Publication Date:
August 02, 1986
Filing Date:
January 26, 1985
Export Citation:
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Assignee:
TOKYO ELECTRON LTD
International Classes:
G01R25/08; (IPC1-7): G01R25/08
Domestic Patent References:
JPS5570750A1980-05-28
Attorney, Agent or Firm:
Shoichi Unemoto