Title:
PHASE-FIXED LOOP OF STATE MACHINE
Document Type and Number:
Japanese Patent JPH06104739
Kind Code:
A
Abstract:
PURPOSE: To eliminate synchronization-related risks, performance defects, and cost which are related to of the conventional technology on synchronizing the phase of a first signal to that of a second signal by synchronously repeating the expansion of the phase of the first signal by a prescribed amount, when the predetermined phase relation between first and second signals is detected. CONSTITUTION: A reference clock signal is inputted to a primary phase detector 34 through a chip lead 31 and an inverter 33, and an internal CPU clock is inputted to a detector 35 through an inverter 35. The phase relation between a data processor clock and a reference clock is detected, when the relation reaches a prescribed state. A phase-correcting signal is inputted to a synchronizer 36 and is synchronous to the domain of a status machine. The reference clock is inputted to a secondary phase detector 41 after the clock is delayed through inverters 37-40 and, at the same time, the internal CPU clock is also inputted to the detector 41 through an inverter 42. The outputs of the detector 41 and synchronizer 36 are inputted to a logic 43. A status machine clock inputted to a chip lead 32 correspondingly to the detected of the prescribed phaseal relation is synchronized to the reference clock by periodically expanding the phase of the machine clock by a prescribed amount.
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Inventors:
LUNDBERG JAMES R (US)
WOLRICH GILBERT M (US)
WOLRICH GILBERT M (US)
Application Number:
JP12140393A
Publication Date:
April 15, 1994
Filing Date:
May 24, 1993
Export Citation:
Assignee:
DIGITAL EQUIPMENT CORP (US)
International Classes:
G06F1/12; G11C11/407; H03L7/00; H03L7/06; H03L7/087; H03L7/099; (IPC1-7): H03L7/00; G06F1/12
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)