位相変動発生回路、及び位相変動発生方法

Title:

位相変動発生回路、及び位相変動発生方法

Document Type and Number:

Japanese Patent JP4206558

Kind Code:

B2

Abstract:

In a phase fluctuation generation circuit and a phase fluctuation generation method, an eight-bit parallel count output from a shift register(653, Fig 3) in a control section 65 is input to a multiplexer 5 as a phase modulated signal, whereby normally the multiplexer 5 functions as a 1/8 division counter. Eight-bit parallel data with the value of "1" shifted by counting up is input from the shift register 653 to the multiplexer 5. The division ratio becomes 1/9 only once. The multiplexer 5 outputs a signal to a phase detector 2 as a phase fluctuation signal with a phase lead of only one clock. May be used for measuring the transmission quality of high speed digital communication system. The output of the phase detector 2 controls a voltage controlled oscillator (VCO) 4.

Inventors:

Kenji Ouri

Application Number:

JP11872799A

Publication Date:

January 14, 2009

Filing Date:

April 26, 1999

Export Citation:

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