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Title:
PHASE INFORMATION DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6477329
Kind Code:
A
Abstract:

PURPOSE: To obtain correct positional information between clocks different in frequency band by using a ring oscillator whose oscillation frequency is synchronized with an input clock as a part for delaying an input clock by means of delay elements of many stages to form multi-phase delay clocks.

CONSTITUTION: The ring oscillator 31 is constituted of connecting gate delay element 61∼64 capable of controlling delay values in series like a loop, a phase error signal is applied from a phase comparing loop filter 30 to the delay value controlling terminals of respective elements 61∼64 and the oscillation output of th ring oscillator part 31 is synchronized with an input clock. Thereby, delay clocks 41∼44 are latched by a latch circuit 24 in accordance with the 2nd frequency clock CK2 having frequency different from that of the 1st frequency clock CK1. The latched clocks are supplied to a conversion table circuit 25 and factors (k), (1-k) are generated in accordance with the contents of the outputs of the latch circuit 24.


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Inventors:
YAMADA MASAHIRO
KAWAI KIYOYUKI
Application Number:
JP23394787A
Publication Date:
March 23, 1989
Filing Date:
September 18, 1987
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03L7/06; G01R25/00; H03H17/00; H03H17/06; H04B14/04; H04L7/00; (IPC1-7): H03H17/02; H03L7/06; H04B14/04; H04L7/00
Domestic Patent References:
JPS62101112A1987-05-11
JPS57115015A1982-07-17
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)