Title:
Phase interpolation clock generation circuit
Document Type and Number:
Japanese Patent JP6337479
Kind Code:
B2
Abstract:
A phase interpolation clock generator includes: a phase detector configured to detect a phase difference between an input signal and a clock; a phase control signal generator configured to generate a phase control signal that is inverted for a certain phase difference and changes between a high level and a low level based on the phase difference; a controller configured to generate a combining control signal for combining a plurality of phase clocks and performing phase interpolation based on the phase control signal; an overshoot detector configured to detect overshoot in which the phase control signal rises above the high level; an overshoot canceller configured to lower the phase control signal which rises above the high level at an occurrence of the overshoot; and a phase interpolator configured to generate the clock by combining the plurality of phase clocks in accordance with the combining control signal.
More Like This:
| JPH11215112 | PLL CIRCUIT |
| JPS6074819 | PHASE SYNCHRONIZING CIRCUIT |
| JP4557947 | Clock data recovery device |
Inventors:
Shiba saki takayuki
Corner Yukito Ta
Corner Yukito Ta
Application Number:
JP2014011641A
Publication Date:
June 06, 2018
Filing Date:
January 24, 2014
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03L7/08; H03K5/00; H03L7/081
Domestic Patent References:
| JP3117028A | ||||
| JP2015133620A | ||||
| JP7297710A | ||||
| JP20038555A | ||||
| JP2010124103A |
Other References:
R. Kreienkamp et al.,A 10-Gb/s CMOS Clock and Data Recovery Circuit With an Analog Phase Interpolator,IEEE JOURNAL OF SOLID-STATE CIRCUITS,米国,IEEE,2004年10月19日,Vol.40, No.3, March 2005,736-743
Attorney, Agent or Firm:
Atsushi Aoki
Koichi Itsubo
Higuchi Souji
Koichi Itsubo
Higuchi Souji