Title:
位相同期回路、送受信回路及び集積回路
Document Type and Number:
Japanese Patent JP7174271
Kind Code:
B2
Abstract:
A phase synchronization circuit which includes a first delay circuit for adjusting a first delay amount, delaying a first reference clock signal by the first delay amount, and outputting a first delayed reference clock signal. The phase synchronization circuit further includes a first clock control circuit that compares phases of the first delayed reference clock signal and a first output clock signal and generates a first clock control signal based on a result of the comparison; a first clock signal generation circuit that generates the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter in the first output clock signal and adjusts the first delay amount based on a result of monitoring the jitter in the first output clock signal.
Inventors:
Tsuge Masatoshi
Application Number:
JP2020529872A
Publication Date:
November 17, 2022
Filing Date:
July 10, 2018
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H03L7/00; H03L7/22; H04B1/403
Domestic Patent References:
| JP2013528011A | ||||
| JP2004153332A | ||||
| JP10032489A | ||||
| JP2003229762A | ||||
| JP2010278720A | ||||
| JP2011171895A | ||||
| JP2015046799A |
Attorney, Agent or Firm:
Kokubun Takaetsu
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