Title:
PHASE-LOCKED LOOP CIRCUIT
Document Type and Number:
Japanese Patent JP2993559
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit which does not generate harmonic synchronization establishment and stably operates even when the same codes continue.
SOLUTION: A delay block 12 delays input data in a prescribed time. When a data change detecting block 13 detects a data change, it outputs a prescribed time window signal. A multiplexer block 18 outputs a VCO clock while a window signal is inputted and outputs a digital logical level as a feedback signal except the time when a window signal is inputted. A phase comparing block 14 detects the phase difference between delay input data and the feedback signal and outputs an output that corresponds to it to a charge pump block 15. An output of the block 15 is given to a VCO 17 through a lowpass filter block 16 and the VCO generates a VCO clock of a frequency that corresponds to it.
More Like This:
| JP2636490 | [Title of Invention] PLL Circuit |
| JP2868063 | PHASE LOCKED LOOP CIRCUIT |
| JPS5574244 | PLL CIRCUIT |
Inventors:
YUUJIN OSARIBAN
SHIMODA AKIFUMI
SHIMODA AKIFUMI
Application Number:
JP8152197A
Publication Date:
December 20, 1999
Filing Date:
March 31, 1997
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03L7/087; H03L7/089; H03L7/14; H04L7/033; H04L7/00; (IPC1-7): H04L7/033; H03L7/14
Attorney, Agent or Firm:
Yosuke Goto (1 person outside)