PURPOSE: To shorten the of the time acquisition of synchronism by switching the frequency dividing ratio of a frequency dividing counter to the value different from that obtained a phase locked loop is stabilized when this loop kept in the process of the acquisition of synchronism.
CONSTITUTION: A phase locked loop circuit constituted of a phase comparator 1, an inverting amplifier 2, a voltage control crystal oscillator 3, a frequency dividing counter 4, the voltage comparators 5 and 6, and a dividing ratio setting circuit 7. The frequency dividing ratio of the counter 4 is switched to the value different from that obtained when a phase locked loop constituted of the comparator 1, the oscillator 3, and the counter 4 is stabilized in the case of the acquisition of synchronism. Thus it is possible to shorten the time of the acquisition of synchronism with a low phase comparison frequency by using the oscillator 3 having an oscillation frequency range where the satisfactory jitter characteristic is secured.
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TANAKA YUTAKA
NISHIZAWA DAIJI
| JPS62257218A | 1987-11-09 |