PURPOSE: To prevent production of a pseudo clock by comparing a phase of a comparison clock signal with a phase of an output of a frequency divider, applying a phase error signal and a frequency error signal to a VCO so as to make the oscillated frequency close to a prescribed value.

CONSTITUTION: A phase comparator 2 compares a phase of a comparison clock signal REF with a phase of an output SD of a frequency divider 9 to output a phase error signal TU and it is inputted to a signal synthesis circuit SM via a switch circuit LP. On the other hand, a frequency phase circuit 3 uses a master clock MC to count a frequency of the output SD and to output frequency error signals FU, FL and they are inputted to the circuit SM and to a gate signal generating circuit GS. The signals TU, FU and TL, FL are sent to a VCO 8 via the circuit SM and a loop filter 7. In this case, while a phase error signal from the comparator 2 is fed to the filter 7, when the frequency error signal is outputted from the comparator 3, the phase error signal is not fed to the filter 7, the oscillating frequency of the VCO approaches a prescribed value to prevent a pseudo clock.