Title:
位相同期回路および位相同期化方法
Document Type and Number:
Japanese Patent JP4807909
Kind Code:
B2
Abstract:
A phase-locked loop (PLL) circuit delays an input clock signal having a first frequency and generates a feedback signal to be delayed with respect to the input clock signal by one cycle. After synchronizing phases of the input clock signal and the feedback signal, a phase comparator compares the phase of the input clock signal with a phase of a reference clock signal having a second frequency, and generates a differential signal corresponding to the phase difference. A counter counts up or down in response to the differential signal. A decoder generates control signals from counting data. A voltage controlled delay line (VCDL) generates an output clock signal by delaying the input clock signal while the control signals are activated. When the phases of the input clock signal and the reference clock signal coincide with each other, the output clock signal from the VCDL has the same frequency with the input clock signal and is synchronized with the reference clock signal. Hence, frequencies of the first clock signal and the reference clock signal can be synchronized with each other by the PLL circuit operation.
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Inventors:
Yellow Sheng Siku
Application Number:
JP2001203103A
Publication Date:
November 02, 2011
Filing Date:
July 04, 2001
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06F1/12; H03L7/081; H03K5/14; H03L7/00; H03L7/087; H03L7/22; H04L7/033; H03L7/089
Domestic Patent References:
| JP2000196424A | ||||
| JP2000101425A | ||||
| JP11177399A | ||||
| JP10276074A |
Attorney, Agent or Firm:
Makoto Hagiwara