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Title:
PHASE LOCKED LOOP SYSTEM IN DIGITAL SIGNAL PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPS6019363
Kind Code:
A
Abstract:

PURPOSE: To detect phase difference by A/D-converting a television signal, holding it digitally, D/A-converting the held signal and controlling a voltage controlled oscillator with this D/A-converted analog signal to have only to latch the output of a specific point of time of the A/D-output.

CONSTITUTION: The input television signal is digitized by an A/D converter 1 and fed to a picture signal processing system and also to a PLL circuit. That is, the signal is set to a latch circuit 3 by the output of a 1/N circuit 2. The 1/N circuit counts N pulses included in one horizontal period and outputs an output gate pulse once at N-times, i.e., once at a horizontal period. This output is D/A- converted by a D/A converter 4 and fed to a VCO6 via an integration circuit 5 during one horizontal period afterward. In this case, when the amplitude of the gated output is too high, it means the oscillated frequency is too low and the control is executed to increase the oscillating frequency of the VCO.


Inventors:
FUKINUKI NORIHIKO
Application Number:
JP12605583A
Publication Date:
January 31, 1985
Filing Date:
July 13, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04N5/04; H04N5/12; (IPC1-7): H04N5/04
Attorney, Agent or Firm:
Akio Takahashi