Title:
PHASE LOCKED LOOP
Document Type and Number:
Japanese Patent JP3313998
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To quickly and stably shift a frequency.
SOLUTION: Frequencies of outputs of a reference signal source 1 and a voltage controlled oscillation circuit 3 are divided by frequency division circuits 2 and 4 respectively. A phase comparison circuit 5 outputs an error signal corresponding to the phase difference between these signals. A window signal is outputted from a window generator circuit 9; and if the error signal is not within its pulse width, a level generator circuit 10 generates a boost voltage close to the control voltage value of the voltage controlled oscillation circuit 3 which is used to generate an objective frequency. A low pass filter circuit 7 receives the output of a charge pump circuit 6 and the boost voltage and is charged, and the control voltage quickly rises to a target value without rising to an excessive value. Thus, undershoot and overshoot are suppressed to quickly stably shift the frequency.
Inventors:
Kikukawa Hirohisa
Application Number:
JP6269197A
Publication Date:
August 12, 2002
Filing Date:
March 17, 1997
Export Citation:
Assignee:
Japan Precision Circuits Co., Ltd.
International Classes:
H03L7/093; H03L7/10; H03L7/187; H03L7/107; (IPC1-7): H03L7/10; H03L7/187
Domestic Patent References:
| JP4101515A | ||||
| JP63124623A | ||||
| JP1098376A | ||||
| JP851360A |
Attorney, Agent or Firm:
Kazuko Matsuda
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