PURPOSE: To read each leading phase in matching with a same read frame even when a phase shift by several multiplex frames is in existence among plural frame processing signals.
CONSTITUTION: The circuit is provided with parallel arrangement double buffer memory switches 101-101n writing a signal sequentially from a head in the unit of multiplex frame, a changeover timing generating circuit 102 generating a double buffer switching timing while delaying the timing one by one multiplex frame, a frame pattern identification circuit 103 detecting a frame bit of each frame processing signal in the multiplex frame processing signal input, an address generating circuit 104 generating a read address of a data string and a frame bit of each frame processing signal and applying them to the memory switches based on frame bit location data of each detected frame processing signal, and a selection control circuit 105 selecting the data string read from the memory switch so that the leading phases are matched.
NANBA KENSABURO
HANAEDA KAZUNORI
WATANABE TORU
TAKEDA SATOSHI
