Title:
PHASE MATCHING CIRCUIT
Document Type and Number:
Japanese Patent JPS6467029
Kind Code:
A
Abstract:
PURPOSE: To resolve the problem of changing the impulse cycle of a clock signal by inhibiting the selection of an arbitrary signal among signals for which a phase matched output signal is delayed from an oscillation signal just for the amount of time longer than the amount of time for delay. CONSTITUTION: A phase matching circuit is provided with the circuit elements of OR gates 245, 247 and 249 and inverter circuits 232, 234, 236 and 238 for surely passing only one clock phase signal through an OR gate 260 when total time delay applied by delay elements 214, 216, 218 and 220 is longer than one cycle of a clock signal CLK. These circuit elements are operated to inhibit the delayed phase of a clock signal, which has time delay longer than the time delay of a selected signal, from passing. Thus, the problem of changing the impulse cycle of the clock signal by introducing an unwanted high frequency signal component into an output clock signal can be canceled.
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Inventors:
DEIBITSUDO ROOUERU MAKUNIIRII
Application Number:
JP19468088A
Publication Date:
March 13, 1989
Filing Date:
August 05, 1988
Export Citation:
Assignee:
RCA LICENSING CORP
International Classes:
H03K5/135; H03L7/081; H03K5/00; H04N5/04; (IPC1-7): H03K5/00; H03K5/135
Domestic Patent References:
| JPS62269410A | 1987-11-21 |
Attorney, Agent or Firm:
Katsunori Watanabe