Title:
PHASE MODULATION PULSE LOGIC GATE OF GALLIUM ARSENIDE
Document Type and Number:
Japanese Patent JPS61123221
Kind Code:
A
Abstract:
A logic system preferably for gallium arsenide integrated circuits uses dynamic pulsed logic gates which switch on each clock pulse, with the logical state of an output or data line being indicated by the phase of the pulsed output, which may be shifted or modulated with respect to a reference. An individual logic gate (1) has a first signal generator having a capacitor (30) which is either charged up or discharged during a set-up phase of a clock cycle, depending upon applied input logic signals. During a second, transmit phase of the clock signal, the signal developed on the capacitor is output from the gate. A second signal generator (112 - 131) is an inverting slave of the first, and outputs the inverse logic state during the succeeding set-up phase of the first generator.
With each gate switching on every clock period, all switching noise appearing in the ground or power supplies is at or above the clock frequency and can simply be filtered out with small chip capacitors, providing improvements in noise immunity.
The logic is preferably implemented in gallium arsenide metal oxide semiconductor technology, with the capacitors formed from reverse-biased Schottky diodes and all FET switches capacitively coupled and self biased.
Inventors:
SHIIMAARU AARU KUREI
Application Number:
JP18594285A
Publication Date:
June 11, 1986
Filing Date:
August 26, 1985
Export Citation:
Assignee:
KUREI RES INC
International Classes:
G06F7/00; H03K19/003; H03K19/096; H03M5/12; (IPC1-7): G06F7/00; H03K19/007; H03K19/096; H03M5/12
Attorney, Agent or Firm:
Kyozo Yuasa (4 outside)