PURPOSE: To provide a phase synchronization control circuit with which time to the establishment of phase synchronization can be shortened and suspended as well.

CONSTITUTION: This circuit is provided with a D flip-flop 2 for outputting the advance or delay of the phase of an output clock signal Fo in respect to a reference clock signal Fr as +1 or -1 for each clock of the reference clock signal Fr. A CPU 11 successively substitutes this output signal of +1 or -1 in a program calculating formula stored in a RAM 12 so that data converged at a fixed value can be provided as the output of the CPU 11 and by converting these data to an analog voltage and controlling a VCXO 1 with this voltage, the phase of the output clock signal Fo of the VCXO 1 can be synchronized with the phase of the reference clock signal Fr. Besides, synchronizing speed can be changed by changing the constant of the program calculating formula as well.