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Title:
PHASE SYNCHRONIZING CIRCUIT
Document Type and Number:
Japanese Patent JPS6298917
Kind Code:
A
Abstract:

PURPOSE: To stabilize an oscillation output by providing a gate circuit and a means using a sampling circuit just after a signal is inputted from a non-signal state to evade the sampling of an output signal of a voltage controlled oscillator whose phase is rotated.

CONSTITUTION: A synchronizing signal detected from a signal fed to a signal input terminal 1 is applied to a differentiation circuit 3, a waveform of a point where an input signal changes from the absence to the presence to a synchronizing detection circuit 2 is prolonged by a multivibrator 4, the non-signal section is prolonged by an OR gate 5a of a gate circuit 5 and a constant level signal CLV is sampled by the 2nd sampling circuit 12. On the other hand, the synchronizing signal is differentiated by the differentiation circuit 3 and the signal outputted from an integration circuit 11 is sampled by the 1st sampling circuit 6. Outputs of the 1st and 2nd sampling circuits 6, 12 are connected in common, the voltage is held by a holding circuit 7 and fed to a loop filter 8, where the harmonics are eliminated, and the result is fed to a VCO 9, and the output signal is frequency-divided so as to have the same frequency as that of the synchronizing signal in the input signal by a frequency divider 10 and the result is outputted to the integration circuit 11.


Inventors:
TSUKANE SHUZO
Application Number:
JP23761885A
Publication Date:
May 08, 1987
Filing Date:
October 25, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03L7/14; H03L7/06; H03L7/10; (IPC1-7): H03L7/06
Domestic Patent References:
JPS59190725A1984-10-29
JPS5717237A1982-01-28
JPS5864753A1983-04-18
Attorney, Agent or Firm:
Masaki Yamakawa