Title:
PHASE SYNCHRONIZING CONTROL DEVICE AND METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3219063
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make it possible to generate a clock signal while reducing a jitter since a phase step out easily occurs and the clock signal including a lot of jitters are easier to be generated when a data signal of the same code continuation is inputted or the like because the clock signal is not fed back.
SOLUTION: When a phase detector(PD) 13 detects a phase difference between a clock signal and an input data signal generated by a gated controlled oscillators(GCO) 11 and 12 and supplies an LPF 16 with it, this LPF 16 supplies the GCO 11 and the GCO 12 with a control signal while phase synchronizing the clock signal with the input data signal; so it becomes possible to prevent step out to the same code continuation and to generate the clock signal with few jitters.
Inventors:
Kentoku Homma
Application Number:
JP31509198A
Publication Date:
October 15, 2001
Filing Date:
November 05, 1998
Export Citation:
Assignee:
NEC
International Classes:
H03L7/08; H03L7/14; H04L7/033; H04L25/40; (IPC1-7): H04L7/033; H03L7/08; H03L7/14; H04L25/40
Domestic Patent References:
| JP1293727A | ||||
| JP7193497A |
Attorney, Agent or Firm:
Kihei Watanabe