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Title:
PHASE SYNCHRONIZING OSCILLATOR CIRCUIT
Document Type and Number:
Japanese Patent JPH04107010
Kind Code:
A
Abstract:

PURPOSE: To improve the power variance characteristic and the temperature characteristic to the oscillation frequency and to prevent step-out by providing a voltage limiting circuit and a limit voltage setting circuit.

CONSTITUTION: The output signal of a voltage controlled piezoelectric oscillator 6 is inputted to a frequency divider 1 and has the frequency divided up to the frequency of a reference signal. The output signal of the frequency divider 1 and the reference signal are inputted to a phase comparator 2, and the phase difference from the reference signal is outputted as a pulse signal. A voltage limiting circuit 3 inputs the pulse signal, which has the peak voltage limited, to a loop filter 5 and smooths it to output a DC voltage signal proportional to the phase difference. Since the circuit 3 is set by a limit voltage setting circuit 4 so that it limits the peak voltage of the pulse signal, a maximum voltage of the pulse signal outputted from the comparator 2 is limited and outputted. Therefore, the variance in amplitude of the pulse signal due to the variance of power or temperature is reduced. Con sequently, the oscillation frequency characteristic is improved to prevent step-out.


Inventors:
FUKUKAWA SHINICHI
Application Number:
JP22614890A
Publication Date:
April 08, 1992
Filing Date:
August 28, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03L7/093; (IPC1-7): H03L7/093
Attorney, Agent or Firm:
Uchihara Shin



 
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