PURPOSE: To set a variable step width of the phase of an output signal with a small-scale and simple circuit by providing a counter, a comparing means, and an output control means.

CONSTITUTION: A counter 11 divides the frequency of an input signal, and an output control means 15 outputs this frequency division output at the output timing obtained by a comparing means 13, therefore, the frequency of the output signal is equal to the frequency of the frequency division output. The output timing is variably set in accordance with the result of comparison between the counted value outputted from the counter 11 and a value given as the select signal by the comparing means 13. Consequently, the shift register which delays the signal preliminarily obtained by frequency division in many stages and the selector which selects the output of this shift register in a conventional circuit are not used to directly generate the output signal, which has the phase varied in accordance with the select signal, while keeping the frequency division ratio constant.