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Title:
PHOTOELECTRON INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0513742
Kind Code:
A
Abstract:

PURPOSE: To provide a light receiving simply to be manufactured OEIC which minimizes noise, and reduces the generation of heat and the consumption of power.

CONSTITUTION: By applying positive or negative voltage to this bias electrode, a horizontal type light receiving device 12 is made capable of confining both carriers optically generated in a light receiving layer into its interior or taking out one party of carriers and controlling the sensibility of the device. The output of the horizontal type light receiving device 12 is input into a level detection circuit 18 so that it may be possible to obtain a flattened voltage signal. This voltage signal is reversely amplified in a bias amplifier circuit 20 and enters a bias electrode as bias voltage. When the average level of the detection signals rises and drops, depending on the strength of optical pulses which enter the horizontal type light receiving device 12, the bias voltage which enters the bias electrode is reduced and increased accordingly. It is, therefore, possible to increase and reduce the sensibility based on the operating characteristic of the horizontal type light receiving device 12 and carry out automatic gain control(AGC).


Inventors:
TATO NOBUYOSHI
Application Number:
JP16176991A
Publication Date:
January 22, 1993
Filing Date:
July 02, 1991
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H01L27/146; H01L27/15; (IPC1-7): H01L27/146; H01L27/15
Attorney, Agent or Firm:
Yoshiki Hasegawa (3 outside)



 
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