To realize speeding up of circuit simulation and decrease of data quantity by reflecting in hierarchical circuit information the physical information extracted from layout information while maintaining a hierarchy structure, generating hierarchical circuit information with physical information, and thus reflecting to the circuit information of the hierarchical structure while maintaining accuracy.
This method includes a physical information extraction process for extracting information regarding physical condition in a single unit such as element, cell, such as a parasitic element, a parasitic coupling element, a shape parameter of a device, and performance or property of the device, from layout information, or physical information and a physical information reflection process for reflecting the physical information to the circuit information consisting of hierarchy and acquiring the hierarchical circuit information while maintaining the hierarchical structure.
TANAKA MASAKAZU
ITO MASANORI
Toshimitsu Ichikawa
Kimihide Hashimoto
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