Title:
PICTURE AND DATA MULTIPLEX CIRCUIT
Document Type and Number:
Japanese Patent JP3152515
Kind Code:
B2
Abstract:
PURPOSE: To provide a picture and data multiplex circuit in which data can be reproduced without deteriorating a picture quality in a conventional decoder, and the erroneous detection of data by an encoding and decoding can be evaded.
CONSTITUTION: Picture data divided into blocks of a specific size by a block dividing circuit 101 are transformed into encoding coefficients corresponding to frequency components by an orthogonal transformation circuit 102, and quantized by a preliminarily set numeric value by a quantizing circuit 104. Then, the other data are multiplexed on the high frequency component area of the encoding coefficients after quantization by a multiplex circuit 105.
Inventors:
Yoshinobu Yamakita
Application Number:
JP24327392A
Publication Date:
April 03, 2001
Filing Date:
September 11, 1992
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H03M7/30; G06T9/00; H04N1/387; H04N1/41; H04N7/08; H04N7/081; H04N7/24; H04N19/00; H04N19/423; H04N19/60; H04N19/625; H04N19/70; H04N19/85; (IPC1-7): H04N7/24; H04N1/41; H04N7/08
Domestic Patent References:
| JP339789A | ||||
| JP686270A |
Attorney, Agent or Firm:
Masamasa Shibano