PURPOSE: To compose a relatively large-scale circuit of general logical circuits, by switching one counter successively for a change in frequency division rate and generating a 4-frequency pilot signal from one reference signal, and generating a timing pulse group whose phase error is suppressed to the precision of the reference signal as the 2nd reference signal.

CONSTITUTION: A 378 fH reference signal CLK is supplied to a 4-frequency pilot signal generating circuit 1, the 5th pilot signal f5 generating circuit 2, and a PG edge detecting circuit 3. An f5 record timing pulse f5 generating circuit 2, an f5 reproduction timing pulse f5 PB, and an output control signal CNT control a pilot signal output circuit 4 so that pilot signals f1Wf4 are continuous or intermittent waves. A timing pulse generating circuit 6 outputs two recording head switching pulses REC.HSW1 and REC.HSW2, a reproducing head switching pulse PB.HSW, an f5 recording timing pulse f5 REC, and an f5 reproduction timing pulse f5 PB as the timing pulse group.