To provide a pipeline processing device which establishes synchronization in a short time.
A dummy signal generation circuit 13 inputs a video signal simultaneously with input to a pipeline processing circuit 11, and generates a dummy signal in which a synchronizing signal which has the same phase as that of the video signal output from the pipeline processing circuit 11 is inserted by using a cycle T of the synchronization signal included in the video signal and a delay time Td from input of the video signal in the pipeline processing circuit 11 to its output. A synchronization detection circuit 15 connects to the dummy signal generation circuit 13 during storing the video signal in the pipeline processing circuit, and detects the synchronization signal from the dummy signal generated in the dummy signal generation circuit 13.
OISHI KAZUO
Iwa Saki Kokuni
Kawamata Sumio
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu
Suzuki Isobe