Title:
画素回路および表示装置
Document Type and Number:
Japanese Patent JP5121114
Kind Code:
B2
Abstract:
When a switching TFT is switched on, a data voltage on a data line is stored in a storage capacitor as a gate voltage of a driver TFT. In this state, a voltage on a pulse drive line is caused to fall. AMOS type capacity element having a second electrode connected to a reference voltage is connected to a gate of the driver TFT. The MOS type capacity element is in an ON state before a fall of the pulse drive line and becomes an OFF state during the fall, and a capacitance changes at the switching of ON state to the OFF state. Therefore, the slope of fall of the gate voltage changes, and the gate voltage after the fall on the pulse drive line can be corrected corresponding to the variation in the threshold values among driver TFTs.
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Inventors:
Keiichi Sano
Maruji Koji
Masayuki Furukawa
Kenya Uesugi
Michiru Senda
Hisahito Yamamura
Maruji Koji
Masayuki Furukawa
Kenya Uesugi
Michiru Senda
Hisahito Yamamura
Application Number:
JP2004154072A
Publication Date:
January 16, 2013
Filing Date:
May 25, 2004
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
G09F9/30; G09G3/30; G09G3/20; H01L51/50; H01L27/32; H05B33/00; H05B33/14
Domestic Patent References:
| JP2004118132A | ||||
| JP11272233A |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida