Title:
保護封筒内にチップモジュールを有する平坦な担体の配置とその配置のための方法
Document Type and Number:
Japanese Patent JP3811677
Kind Code:
B2
Abstract:
A configuration of a flat carrier with a chip module in a padded envelope, which can be transported in a transport device in the direction of one of the envelope's side edges, includes disposing the chip module in the padded envelope such that wire connections in the chip module extend over a side of the semiconductor chip that runs parallel to the transport device. Such a configuration is made possible by the fact that the flat carrier is applied in a standard way to a further carrier, which is folded in a suitable way.
Inventors:
Fleece, manfred
Application Number:
JP2002500326A
Publication Date:
August 23, 2006
Filing Date:
March 21, 2001
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
B42D15/02; G06K19/00; B42D15/10; B65D27/02; G06K19/077; G07B17/00; G06K17/00
Domestic Patent References:
| JP4102260U | ||||
| JP11126238A | ||||
| JP11011492A | ||||
| JP9175060A | ||||
| JP61166885U |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita
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