Title:
PLANAR TYPE HETERO JUNCTION SEMICONDUCTOR PHOTODETECTOR
Document Type and Number:
Japanese Patent JPS61265876
Kind Code:
A
Abstract:
PURPOSE:To produce an APD (Avalanche Photo Diode) with lower noise while improving the breakdown voltage of a guard ring by a method wherein the carrier concentration of semiconductor provided with P-N junction is reduced stepwise in proportion to the distance from the hetero interface. CONSTITUTION:Within this APD, an N-InP buffer layer 2, an N<->-InGaAs layer 3 with narrow forbidden band width and an InGaAs layer 3' with intermediate forbidden band width between the layers 3 and 4 are laminated on an N<+>InP substrate 1. Now in proportion to the distance between the InGaAs layer and the InP formed on these photo-absorbing layers, the carrier concentration is reduced stepwise exceeding three steps in an N1-InP layer 4, an N2-InP layer 4' and an N3-InP layer 4'' (provided N1>N2>N3). Through these procedures of forming N-InP compound layers, the positive curvature on the peripheral part of a guard ring 5' is relieved to improve the breakdown voltage. Moreover an APD with lower noise can be produced by means of locating a step type P<+>-N junction in the N2-InP layer 4'.
Inventors:
TORIKAI TOSHITAKA
Application Number:
JP10863485A
Publication Date:
November 25, 1986
Filing Date:
May 20, 1985
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L31/107; (IPC1-7): H01L31/10
Domestic Patent References:
| JPS52155083A | 1977-12-23 | |||
| JPS59161082A | 1984-09-11 | |||
| JPS58170073A | 1983-10-06 |
Attorney, Agent or Firm:
Yoshiyuki Iwasa (3 others)