Title:
PLASMA ETCHING METHOD FOR SEMICONDUCTOR SUBSTRATE
Document Type and Number:
Japanese Patent JP3501872
Kind Code:
B2
Abstract:
PURPOSE: To decrease the dispersion of etching speed inside a wafer by controlling the etching speed of each part of a semiconductor substrate.
CONSTITUTION: On the occasion of plasma-etching a surface of a semiconductor substrate 1 covering it with an etching mask having a large number of openings, the semiconductor chip nonformation region of a semiconductor substrate 1 surrounding the peripheral brim of the semiconductor formation region along with the semiconductor formation region is covered with an etching mask 2, and slits 21 are formed in a part corresponding to an orientation flat formation part 11 in the peripheral brim of the semiconductor substrate 1, out of the peripheral part of the etching mask 2 covering the semiconductor chip nonformation region, and the area of openings is magnified. Consequently, etching speed in the peripheral brim of the semiconductor chip formation region corresponding to the slits 21 formation parts is lowered.
Inventors:
Takahiko Yoshida
Kazushi Asami
Muneo Yorinaga
Tsuyoshi Fukada
Kazushi Asami
Muneo Yorinaga
Tsuyoshi Fukada
Application Number:
JP12309595A
Publication Date:
March 02, 2004
Filing Date:
April 24, 1995
Export Citation:
Assignee:
株式会社デンソー
株式会社日本自動車部品総合研究所
株式会社日本自動車部品総合研究所
International Classes:
H01L29/84; H01L21/302; H01L21/3065; (IPC1-7): H01L21/3065; H01L29/84
Domestic Patent References:
| JP3266473A | ||||
| JP6455826A | ||||
| JP60201632A |
Attorney, Agent or Firm:
Hirohiko Usui (2 outside)