Title:
PLASMA PROCESSING METHOD
Document Type and Number:
Japanese Patent JPS5612732
Kind Code:
A
Abstract:
PURPOSE:To improve the reproducibility of an etching gas condition by erecting works in the plasma processing chamber in such a manner that the non-processing main surfaces are located so close to each other to prevent the etching thereof. CONSTITUTION:A support base 21 is so arranged that silicon wafers 10, 10... are erected with two as a unit in such a manner that the non-processing main surfaces 10b and 10b' are located close to each other. In other words, the cilicon wafers 10 and 10' are arranged back to back with the non-processing main surfaces thereof close to each other. The surfaces are little subjected to the etching while the main surfaces to be processed are erected exposing in the plasma processing chamber and subjected to the etching. In this manner, the wafers are so arranged adjacent to each other that all surfaces to be processed are subjected to plasma etching simultaneously. This can prevent simultaneous etching of the non-processing main surfaces thereby improving the reproducibility of the etching gas condition. Thus, possible side etching can be checked.
Inventors:
KIKUCHI SADATAKE
OKANO JIYUNICHI
HAMAGUCHI TAKEO
OKANO JIYUNICHI
HAMAGUCHI TAKEO
Application Number:
JP8651579A
Publication Date:
February 07, 1981
Filing Date:
July 10, 1979
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
B01J19/08; H01L21/205; H01L21/302; H01L21/3065; (IPC1-7): B01J19/00; H01L21/205