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Title:
プラズマ増強型化学蒸着基板処理チヤンバ
Document Type and Number:
Japanese Patent JP4014233
Kind Code:
B2
Abstract:
A susceptor or other semiconductor wafer (35) processing and/or transfer support platform (65) includes a surface pattern having two or more regions of high and low elevation. The regions of high and low elevations can be rectangular/square dimpled patterns having tops coplanar with one another to support a semiconductor wafer (35) for processing. The high and low regions can also be a wave form appearing to emanate from a point, where each of the wave crests form an imaginary plane on which a wafer to be processed can rest. The combination of high and low regions increases the average spacing between the wafer and the susceptor and reduces or eliminates the capacitive coupling (or sticking force) between processing hardware and a substrate (wafer) created by electrical fields during processing. The dimpled patterns are created by machining and can be created by using chemical and electrochemical etching of the wafer handling surfaces of processing hardware pieces.

Inventors:
Mark A. Foda
Craig A. Barcau
Charles Dawnfest
Application Number:
JP12023095A
Publication Date:
November 28, 2007
Filing Date:
May 18, 1995
Export Citation:
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Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
B23Q3/15; H01L21/683; H01L21/205; H01L21/302; H01L21/3065
Domestic Patent References:
JP56933A
JP4238882A
JP3179735A
JP4206545A
JP2144934A
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yuichi Yamada