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Title:
PLASTIC PIN GRID ARRAYED PACKAGE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JPH05226513
Kind Code:
A
Abstract:

PURPOSE: To provide the title plastic PGA package capable of loading a semiconductor chip in high calorific value by a method wherein multiple conductor pattern layers are formed for multiple pins as well as for increasing the heat dissipation capacity of a package.

CONSTITUTION: The plastic (PGA) package is integrally junctioned with a metallic core 14, one or multiple lead frames 16 formed into a specific lead pattern and a copper foil 18a formed into a specific circuit pattern holding an electrically insulating semiconductor 12 between layers. On the other hand, a cavity for loading a semiconductor chip 34 is formed on the side wherein the lead frame 16 of the metallic core 14 and the copper foil 18a are provided so that lead pins 30 connecting to the lead frame 16 or the copper foils 18a may be inserted into a through hole for passing package main body therethrough in the thickness direction.


Inventors:
TANAKA MASATO
Application Number:
JP5891392A
Publication Date:
September 03, 1993
Filing Date:
February 12, 1992
Export Citation:
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Assignee:
SHINKO ELECTRIC IND CO
International Classes:
H01L23/12; H01L23/50; (IPC1-7): H01L23/12; H01L23/50
Attorney, Agent or Firm:
Takao Watanuki (1 outside)



 
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