Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PLD LOGICAL SIMULATOR
Document Type and Number:
Japanese Patent JPH03219367
Kind Code:
A
Abstract:

PURPOSE: To constitute the PLD logical simulator without using a PLD logical operation part by fixing the input of a corresponding gate to the disconnected state of a fuze to express the disconnection of the PLD fuze.

CONSTITUTION: The 2nd line of a fuze map/input fixed value corresponding table 6 indicates that when the 2nd request of a fuze map 4 is '1', a developed net list 5 fixes the input 11 of a logical gate G3 in a PID net list 2 to status values '1'. The 1st line 24 in a gate input value fixing information 9 outputted from a gate input value fixing information forming means 8 indicates that the fixed value '1' is set up in the A3/G3:14 of simulation data 13 in a logical simulation means 12 and a gate input value fixing means 10 sets up a fixed value in accordance with the set value. The means 12 executes logical simulation and outputs an output pattern 13 based upon the prepared simulation data 13 and an input pattern 11. Consequently, the PLD logical operation part can be omitted and the structure can be simplified.


Inventors:
TANAKA TOSHIAKI
Application Number:
JP1519790A
Publication Date:
September 26, 1991
Filing Date:
January 24, 1990
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F11/26; G06F15/60
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)