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Patent Searching and Data


Title:
PLL CHANNEL SELECTOR
Document Type and Number:
Japanese Patent JPS632417
Kind Code:
A
Abstract:

PURPOSE: To increase the number of phase-compared frequencies so as to make a control voltage converging time shorter, by causing a channel selection controlling section to temporarily reduce the dividing ratios of both a channel selection divider and reference-frequency divider from those of normal times at the time of channel selection.

CONSTITUTION: When a channel selection operating section 5 is operated and a channel selection controlling section 4 respectively transfers dividing ratios 1/2M' and 1/2L to a channel-selection divider 3 and reference frequency divider B, the dividing ratios of the dividers 3 and 8 are changed to 1/2M' and 1/2L, respectively. Then the frequency from the divider 8 to a phase comparator 6 is doubled and the frequency from the divider 3 is increased by 2M'/M times. This phase difference (frequency difference) produces a Voltage across the comparator 6 and the voltage is smoothed by means of an active LPF 9. As a result, a control current fluctuates and the phase difference which is added to the comparator 6 when t=T1 becomes twice as large as conventional one. Therefore, the changing speed of then control voltage becomes higher than conventional speed and the time from T1 to T2 is shortened. In other words, when the dividing ratios of the dividers 3 and 8w are temporarily reduced to the same ratio from those at normal times, the control voltage converging time can be reduced.


Inventors:
KATO HIROSHI
Application Number:
JP14529386A
Publication Date:
January 07, 1988
Filing Date:
June 20, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03J7/18; H03L7/18; (IPC1-7): H03J7/18; H03L7/18
Domestic Patent References:
JPS60158714A1985-08-20
Attorney, Agent or Firm:
Tomoyuki Takimoto