To provide a PLL circuit device which intermittently compares phases not in the whole period of an input period but in a partial period in the input period and executes PLL on the horizontal synchronizing signal of a television signal, etc.

The horizontal synchronizing signal Hsync and a reference signal Href are phase-compared in a phase comparison circuit 12 and a selector 30 is controlled in accordance with the result, so that Href or one output of the phase comparison circuit 12 is selected. The phase comparison circuit 12 detects a difference between the frequencies fHsyuc and fHref of Hsync and Href. When fHref is lower than fHsync, a switching circuit 26 is closed with the output of an AND circuit 24 and voltage given to a voltage controlled oscillator(VCO) is boosted. When fHref is higher than fHsync, 'L' is fixed and inputted to a NOT circuit 23. The phase of Href is made to always lead, Hsync and the frequency of VCO is controlled to be reduced.