PLL CIRCUIT AND METHOD FOR CONTROLLING VARIABLE DELAY LINE CONSTITUTING THE SAME

Title:

PLL CIRCUIT AND METHOD FOR CONTROLLING VARIABLE DELAY LINE CONSTITUTING THE SAME

Document Type and Number:

Japanese Patent JP2007295182

Kind Code:

A

Abstract:

To suppress the occurrence of jitters in a PLL circuit by setting oscillation ranges to be overlapped at an optional width.

An oscillation control circuit 2 in a digital PLL circuit 10 is provided with a counter control circuit 11, a first up/down counter 12 and a second up/down counter 13. The counter control circuit 11 inputs a control signal Smup which can execute up-counting by skipping e.g., without gradually up-counting a control signal Scn, when a control signal Scm is changed, from a state of a certain value M=X into a state of M=X+1 and a control signal Smdn which can down-count by skipping e.g., without gradually down-counting the control signal Scn, when the control signal Scm is changed from a state of a certain value M=X+1 into a state of M=X. Thereby delay signals can be overlapped at an optional width, independently of the manufacturing dispersions and variations in the temperature, power supply voltage or the like.

Inventors:

KIKUCHI HARUHIDE

Application Number:

JP2006119350A

Publication Date:

November 08, 2007

Filing Date:

April 24, 2006

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

H03L7/099; H03K3/03; H03K5/131; H03K5/14; H03L7/06

Attorney, Agent or Firm:

Hiroshi Horiguchi

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