Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP2002009617
Kind Code:
A
Abstract:
To provide a PLL circuit that can be reduced in size, at a low cost.
The PLL circuit 10 includes a 1st voltage-controlled oscillator 12a and a 2nd voltage-controlled oscillator 12b, whose frequency bands differ from each other, and respective output terminals are connected to one input terminal of a phase comparator 16 via a frequency divider 14. A reference signal is given to the other input terminal of the phase comparator 16. The output terminal of the phase comparator 16 is connected to the input terminals of the 1st voltage controlled oscillator 12a and the 2nd voltage controlled oscillator 12b via a charge pump 18 and a loop filter 20. The current value of a charging/discharging signal outputted from the charge pump 18 is variable.
Inventors:
TAMAKOSHI OSAMU
SUGIMURA TAKASHI
SUGIMURA TAKASHI
Application Number:
JP2000189126A
Publication Date:
January 11, 2002
Filing Date:
June 23, 2000
Export Citation:
Assignee:
MURATA MANUFACTURING CO
International Classes:
H03L7/18; H03L7/099; (IPC1-7): H03L7/18; H03L7/099
Attorney, Agent or Firm:
Okada
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