To realize a PLL circuit to which a recording signal to be recorded in a plurality of different kinds of recording modes is inputted and from which a signal of high purity resulting from removing a noise component included in the input signal.

The PLL circuit is configured as follows; the input signal is frequency-divided into 1/L to output a first frequency signal from a first frequency divider 41, and a master clock signal corresponding to the input signal is oscillated by an oscillator 46a, and the master clock signal is frequency-divided into 1/M to output a second frequency signal from a second frequency divider 52, and a phase difference signal between the first frequency signal and the second frequency signal is outputted from a phase comparator 43, and it is detected by a lock detector 44 whether the first frequency signal and the second frequency signal coincide with each other or not, and L of the first frequency divider and M of the second frequency divider are varied in the case of non-coincidence, and a control signal for fixing L and M is outputted from a control circuit 48 in the case of coincidence, and the master clock signal is frequency-divided into 1/N to output a true signal component from a third frequency divider.