Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP2015220494
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a PLL circuit capable of lengthening a stop time of circuit operation while maintaining frequency change of an output signal when the PLL circuit is locked within a desired range.SOLUTION: A PLL circuit 1 comprises: a reference oscillator 11 which outputs a reference signal; a voltage-controlled oscillator 12 which outputs a first oscillation signal on the basis of a frequency control signal; a frequency divider 13 which divides a frequency of the first oscillation signal and outputs a second oscillation signal; a phase comparator 14 which outputs a phase difference signal corresponding to the phase difference between the reference signal and the second oscillation signal; a low-pass filter 16 which outputs a smoothing signal which extracted a lower frequency than a prescribed frequency from the phase difference signal; a switch 15 which switches the state between the phase comparator 14 and the low-pass filter 16 to a short-circuit state or an open state; a correction voltage generator 18 which generates a correction voltage signal which corrects the amount of change of the smoothing signal when the switch 15 is set to the open state; and an adder 20 which adds the smoothing signal and the correction voltage signal, and outputs the addition result to the voltage-controlled oscillator 12 as a frequency control signal.
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Inventors:
SHINOZUKA TOSHIYUKI
Application Number:
JP2014100532A
Publication Date:
December 07, 2015
Filing Date:
May 14, 2014
Export Citation:
Assignee:
NIHON DEMPA KOGYO CO
International Classes:
H03L7/18; H03L1/02; H03L7/093
Attorney, Agent or Firm:
Izumidori