Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP3404332
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To contrive to match the phase of the leading edge of a reference signal with the phase of the trailing edge of a feedback signal with good accuracy, by a method wherein a differential system of buffers are used for the input part of a PLL circuit for skew adjustment to adjust the phases of the inputs of a delay circuit and a frequency dividing circuit.
SOLUTION: A reference signal is inputted in a first differential buffer 21, at the same time a feedback signal is inputted in a second differential buffer 22 to input the output of the buffer 21 in a delay circuit 23, and the output of the buffer 22 is inputted in a frequency dividing circuit 24. The output of the circuit 23 and the output of the circuit 24 are inputted in a phase comparator 25, and an error signal to respond to the phase difference between the inputs of these two circuits 23 and 24 is outputted to a filter circuit 26 and a voltage control circuit 27. Moreover, the output of the circuit 27 is fed back to the buffer 22 as a feedback signal via a CTS 28.
Inventors:
Masafumi Kurokawa
Kenichi Kawakami
Kenichi Kawakami
Application Number:
JP24267199A
Publication Date:
May 06, 2003
Filing Date:
August 30, 1999
Export Citation:
Assignee:
NC Microsystem Co., Ltd.
International Classes:
H01L21/822; H01L27/04; H03L7/08; (IPC1-7): H03L7/08; H01L21/822; H01L27/04
Domestic Patent References:
| JP5216556A | ||||
| JP9102739A |
Attorney, Agent or Firm:
Hiroshi Amano