PURPOSE: To reduce jitter by stabilizing a frequency of a clock signal outputted from a VCO circuit even when jitter in an external reference signal is large.

CONSTITUTION: A phase comparator circuit 1 detects a phase difference between an external input signal and a feedback signal, a PNM circuit 2 quantizes the result of detection to generate a frequency control data, a moving average filter circuit 3 applies moving average processing to the frequency control data to eliminate a high frequency component and to extend the length of word thereby reducing noise. Then a D/A converter circuit 4 applies D/A conversion to the frequency control data processed by the moving average filter circuit 3 to generate a frequency control signal. Thus, the oscillating frequency of a VCO circuit 5 is controlled based on the frequency control signal to generate a clock signal in response to the content of control and an output timing of a feedback signal outputted from a timing generator circuit 6 is controlled based on the clock signal.