PURPOSE: To provide a PLL circuit capable of obtaining control voltage whose harmonic is reduced even when the time constant of a capacitor in an LPF is small and having a short frequency switching time.

CONSTITUTION: This PLL circuit is provided with plural error voltage generating circuits 14 to 16 each of which generates voltage proportional to the pulse width of each inputted error pulse synchronously with the error pulse and forms each voltage as a step-like waveform to use it as an error voltage, a low pass filter LPF 17 for removing the high frequency component of error voltage and outputting the component-removed output, and an amplifier 18 for outputting a difference between bias voltage outputted from a D/A converter 20 based on data corresponding to objective oscillation frequency and an output voltage from the LPF 17 to a voltage control oscillator 3 as control voltage.