PURPOSE: To reduce the phase error by confirming it that the PLL is locked to regard a protection circuit to be entering a steady-state and increasing an amplification factor of an amplifier according to the superiority of the result of phase comparison by the protection circuit and a phase comparator circuit.

CONSTITUTION: The locking of the PLL is confirmed when the deterioration in a duty cycle of the output of a phase comparator circuit 2 in the PLL circuit is set within a predetermined value consecutive for a predetermined time and a protection circuit 7 is regarded to be entering a steady-state. An amplification factor control circuit 8 changes an amplification factor of an amplifier 4 according to the superiority of the phase comparison result by the circuits 7, 2. A phase error is reduced in the steady-state according to equation of T=/-(A.Kd.KO) by increasing the amplification factor A of the amplifier 4, where T is a steady-state phase error, A is an amplification factor, is a tuning frequency deviation. Kd is a detection gain and KO is a loop gain.