PURPOSE: To attain a small dividing ratio by dividing a decimal point in order to set the finer frequency and also to secure a high response of a PLL circuit for a frequency synthesizer.

CONSTITUTION: A direct digital synthesizer 50A uses the intermediate frequency fCO=fout-fLO which is lower than the oscillation frequency fout of a voltage control oscillator 40 by a degree equal to the local oscillation frequency fLO. Then the synthesizer 50A applies the cumulative addition to a dividing ratio 1/N=N/2n in each clock cycle 1/fCK to output a discrete digital signal S7 of frequency fDDS=(N/2n).fCK.A multiplying DA converter 20A performs the multiplication of the signal S7 and an analog reference signal S1 of frequency fref to output an analog error signal S2 which is proportional the phase difference θbetween both signals S7 and S1. Thus the oscillation frequency fout=(2n/N).fref+fLO is obtained in a phase locked state.