Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JPH09307433
Kind Code:
A
Abstract:
To provide a PLL(phase locked loop) circuit which can shorten the time when the phase difference gets near zero and also can increase the loop operation speed.
A phase/frequency detection circuit 16 decides whether the phase difference between a reference signal SREF and a comparison signal SV is included in a 1st area set between -π/2 and +π/2 or in a 2nd area getting out of the 1st area. If the phase difference is included in the 2nd area (excluding ±π/2), a phase inverting circuit 17 outputs a comparison signal SV having its inverted phase.
Inventors:
SATO YOSHIHIDE
Application Number:
JP11644696A
Publication Date:
November 28, 1997
Filing Date:
May 10, 1996
Export Citation:
Assignee:
FUJI XEROX CO LTD
International Classes:
G01R23/06; G01R25/00; H03L7/081; H03L7/085; H03L7/087; H03L7/10; (IPC1-7): H03L7/081; G01R23/06; G01R25/00; H03L7/085; H03L7/087; H03L7/10
Attorney, Agent or Firm:
山田 正紀 （外１名）