PURPOSE: To obtain a stable clock signal synchronized with an input signal, by inputting the input signal with a delay to a phase comparison circuit, inputting an output of a voltage controlled oscillating circuit via a gate circuit as another input and eliminating an output of the oscillating circuit if the input signal is missing.
CONSTITUTION: The input signal (a) is inputted to the phase comparison circuit 1 after being delayed by a time tD. An output (e) of the oscillating circuit 3 and an output (c) of a monostable FF synchronized with the rise of the input signal (a) and outputting a signal having a pulse width tw including 1/2 cycle length of the output (e) are inputted to a gate element 8. When the input signal is missing, an output of the circuit 1 becomes a high impedance and a voltage before the input signal is missing is held by a loop filter 2, then the oscillating frequency of the circuit 3 is unchanged. When the phase of the output (e) is advanced more than the phase of the input signal the fixing of the oscillating frequency in the advanced state is prevented by giving a delay to the input signal (a), to oscillate the input signal (a), and the phase in synchronization with each other.
ISHIGURO HIDEO
MATSUO NAOKI
AMAMIYA FUJIO
NIPPON TELEGRAPH & TELEPHONE
| JPS5383560A | 1978-07-24 |
Next Patent: PHASE LOCKED LOOP CIRCUIT