Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JPS6424691
Kind Code:
A
Abstract:
PURPOSE:To obtain a PLL output signal with high accuracy by providing a frequency division circuit, a circuit comparing the phase of an input signal whose phase is inverted at a prescribed period and that of an output signal of the frequency division circuit and an oscillation circuit whose oscillating frequency is controlled by the output signal and supplying the output signal to the frequency division circuit. CONSTITUTION:Only one period is extracted from an output signal of a waveform division shaping circuit 3 by a burst wave extraction circuit 5. The extraction is applied based on the front or rear edge of a horizontal synchronizing signal based on a timewise reference. Moreover, a signal obtained by frequency-dividing a horizontal synchronizing signal at a 1/2 frequency division circuit 7 is fed to the circuit 5 to switch the said extracted position for each horizontal synchronizing period. The phase of the output signal of the circuit 5 is compared with the phase of the output signal of the frequency division circuit 10 by a phase comparator circuit 6 and the frequency of a 4fsc oscillator 8 is controlled by the result of comparision. The oscillated frequency is set to 910H, that is, 4fsc. The circuit 10 is switched for each of one horizontal synchronizing period for 1/909 frequency division and for 1/911 frequency division. Then the output signal of the circuit 10 is a signal rising for each one horizontal syncrhonizing period based on the output.
Inventors:
KAWANAKA RYUTA
Application Number:
JP18186387A
Publication Date:
January 26, 1989
Filing Date:
July 21, 1987
Export Citation:
Assignee:
NIPPON DENKI HOME ELECTRONICS
International Classes:
H04N9/45; H03L7/18; H03L7/183; (IPC1-7): H03L7/18; H04N9/45