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Patent Searching and Data


Title:
PLL DETECTOR
Document Type and Number:
Japanese Patent JPH03166805
Kind Code:
A
Abstract:

PURPOSE: To obtain constitution which is stable in circuit mounting by setting the oscillation frequency of a voltage-controlled oscillator(VCO) to 1/n or (n) times the input frequency of the detector.

CONSTITUTION: A detection input signal which is supplied to an input terminal 1 is inputted to a double balanced mixer circuit 5 through a 1st amplifier 2, a BPF 3, and a 2nd amplifier 4. The output oscillation signal of the VCO circuit 7 of an PLL circuit is supplied to the circuit 5, whose output signal is outputted from an output terminal 8 through an LPF 6. At the same time, the circuit 7 is controlled with the DC voltage of the output signal of the LPF 6 to set the oscillation frequency. The free-run oscillation frequency of this circuit 7 is set to 1/n or (n) (n: integer large than 2) times the detector input frequency. The oscillation frequency of the circuit 7 which is determined under the voltage control is locked in phase with the detector input frequency by the circuit 5 to become 1/n or (n) times the input frequency.


Inventors:
YAMAKAGE YOICHI
Application Number:
JP30492889A
Publication Date:
July 18, 1991
Filing Date:
November 27, 1989
Export Citation:
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Assignee:
KENWOOD CORP
International Classes:
H03D3/02; (IPC1-7): H03D3/02
Domestic Patent References:
JPS57148910U1982-09-18



 
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