Title:
PLL DEVICE FOR PULSE DEMODULATION
Document Type and Number:
Japanese Patent JP3553753
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable a PLL circuit to reduce a frequency of an operation clock that detects a pulse.
SOLUTION: A pulse detecting part 10 samples a pulse signal to be demodulated, based on an operation clock. An operation clock generating part 9 generates an operation clock, so that the cycles for pulse precision (n) enters in a the pulse width to be demodulated. The phase relations of operation clocks and pulses are divided into six types of patterns, and when a relation is not included in the patterns, it is excluded while being judging that it is due to noise effects. A pulse detection signal which eliminates noise effects is given from the part 10 to a phase comparison part 11, compared with a reproducing clock timing signal, that shows the timing of a reproducing clock which is generated by a clock-reproducing part 12, and a control signal that performs phase control of the part 12, is generated.
Inventors:
Masahiro Otani
Application Number:
JP1916297A
Publication Date:
August 11, 2004
Filing Date:
January 31, 1997
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H03K23/66; H03K9/04; H03L7/14; H04L7/033; H04L25/49; H04L27/14; H03L7/06; (IPC1-7): H03K9/04; H03K23/66; H03L7/14; H04L27/14
Attorney, Agent or Firm:
Keiichiro Saikyo