Title:
PLL FREQUENCY SYNTHESIZER CIRCUIT, COMPARISON FREQUENCY DIVIDER AND SWALLOW COUNTER
Document Type and Number:
Japanese Patent JP3468964
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent malfunction of a prescaler for the operation delay of a swallow counter and to enable a high speed operation.
SOLUTION: A swallow counter is provided with a malfunction prevention circuit part 42. When all the set value data A1 to A7 supplied from a shift register 33 is '0', the malfunction prevention circuit 42 does not output a modulus signal MDC even if a load signal LOAD is not outputted. A NOR circuit 43 inputs the set value data A1 to A7 from the shift register 33 and supplies a decision signal SG to a first DFF 44 only when all of the contents is '0'. The first DFF 4 responds to a strobe signal STB and supplies the fourth output signal SGI at the time to the data input terminal of a second DFF 45. The second DFF 45 responds to the load signal LOAD and supplies the fifth output signal SG 2 of the level inverted from the fourth output signal SG 1 to a D type flip flop 40.
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Inventors:
Tetsuya Aisaka
Application Number:
JP1332996A
Publication Date:
November 25, 2003
Filing Date:
January 29, 1996
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
H03L7/197; H03K21/40; H03K23/66; H03L7/08; H03L7/183; H03L7/193; (IPC1-7): H03L7/183; H03K21/40; H03L7/08
Attorney, Agent or Firm:
Hironobu Onda
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